1. Field of the Invention
The present invention relates generally to the field of electronics and particularly to charge pumps for phase locked loops in microprocessors.
2. Description of the Related Art
Phase locked loops are a well known form of circuit useful in synchronizing a clock signal internal to a circuit with an external clock signal. The block diagram of FIG. 1 represents a generally well understood design for such a phase locked loop.
FIG. 1 shows a high level design for a phase locked loop. Phase Detector 102 receives a Ref Clock 101 and a Feedback Clock signal 112, which is fed back through the loop. Phase Detector 102 compares Ref Clock 101 with Feedback Clock 112 and generates an Up signal 103 and a Down signal 104. Charge Pump 105 receives Up signal 103 and Down signal 104 and generates an Ipump signal 106. Loop Filter 107 receives Ipump signal 106 and converts Ipump signal 106 to Vcontrol signal 108. VCO 109 receives Vcontrol signal 108 and generates Internal Clock signal 110. Divide-by-N 111 receives Internal Clock signal 110 and divides Internal Clock signal 110 by a designed in factor N to generate Feedback Clock 112. Feedback Clock 112 is fed back into the Phase Detector 102 as described above, such that the Internal Clock signal 110 eventually is a multiple of Ref Clock 101.
One disadvantage of the prior art scheme illustrated in FIG. 1 involves the current sources used to add or subtract current in Charge Pump 105. If these sources do not deliver the same current over all operating conditions then the up and down signals 103 and 104 produced by phase detector 102, even if perfectly matched, will produce some sort of error current which will be erroneously added to or subtracted from the capacitor in loop filter 107.
One prior art solution involves circuit designers attempting to size all devices involved such that the currents match as closely as possible according to the models of the semiconductor process available. Sizing all devices for matched performance suffers from two problems, both well known in the prior art. First, models predict how a circuit will behave, but these models are often incorrect in their predictions. Second, processes vary over time in any manufacturing environment, and these variations produce irregularities in the size of devices. Circuit designers and layout engineers can place critical components together to reduce the differences in these variations, but these efforts to avoid process variations are limited in their effectiveness.
Another prior art method of dealing with the charge pump problem involves optimizing the circuit for operation around the expected operating point. This method also has drawbacks. First, optimization depends on the same models that the sizing method depends on, so optimization will often not lead to the best result in practice. However, no amount of modeling can predict what apparently suboptimal design will produce the optimal product until after production occurs. Second, operating points of circuits vary with factors often beyond the control of the designer, such as temperature, power supply variations, and in the case of phase locked loops external clock frequency. Any commercially viable product will have to operate over enormous ranges of temperature and power supply at a minimum, and optimization can only occur for one operating point.
FIG. 2 shows a general diagram of a prior art charge pump for a phase locked loop. Up Current Source 201 supplies a current. Coupled in series with Up Current Source 201 is Up Switch 202, which is controlled by Up signal 203 and Upbar Switch 205, which is controlled by Upbar signal 204. Coupled to Up Switch 202 is Down Switch 209, which is controlled by Down signal 208. Coupled in series with Upbar Switch 205 is Downbar Switch 211, which is controlled by Downbar signal 210. Coupled in series with Down Switch 209 and Downbar Switch 211 is Down Current Source 212, which supplies (or sinks) a current. Voltage node Vcontrol 206 is disposed between Up Switch 202 and Down Switch 209. An OpAmp 207 has its positive input coupled to Vcontrol 206. OpAmp 207 has its output and its negative input coupled to a voltage node between Downbar Switch 211 and Upbar Switch 205.
Voltage node Vcontrol 206 is coupled to Loop Filter 107 of FIG. 1. The current supplied through Up Switch 202 and Down Switch 209 is the current signal Ipump 106 of FIG. 1. By charging or discharging a capacitor (not shown) in Loop Filter 107, current signal Ipump 106 is converted to voltage Vcontrol 108 of FIG. 1.
One problem with the charge pump illustrated in FIG. 2 is that the problem of current sources 201 and 212 not delivering the same amount of current over all operating conditions is not addressed. Thus, what is desired is a charge pump such that the currents delivered by the current sources are substantially equal over a variety of operating conditions.